1. Field of the Invention
This invention relates to EPROM memory devices and more particularly to enhancement mode EPROM and flash EEPROM devices and method of fabrication of such devices.
2. Description of Related Art
Two level polysilicon cells with a split or overlapping gate electrode are generally known and used in a variety of applications.
EPROM (Erasable Programmable Read Only Memory) FET devices provide long term retention of charge to store data. The charge is stored on a floating gate electrode which is not electrically connected to a terminal. Instead, the charge is supplied to the floating gate electrode through an insulator. The data may be erased by exposure of the device to ultraviolet light to erase the stored data by discharging the floating gate electrode.
EEPROM (Electrically Erasable Programmable Read Only Memory) FET devices can be erased by electrical means instead of exposure to ultraviolet light.
Flash EPROM devices are EEPROM FET devices with a double gate electrode structure including a floating gate electrode and a control gate electrode. The device includes a tunnel oxide dielectric layer between the substrate and the floating gate electrode by a thickness of about 100 .ANG. and an interelectrode dielectric layer about 200 .ANG.-250 .ANG. thick composed of silicon oxide or ONO.
U.S. Pat. No. 4,313,253 of Henderson for "Method for Fabricating a Charge Transfer Channel Covered by a Stepped Insulating Layer" shows a P-channel, split gate electrode memory cell having double level polysilicon cell with heavily doped polysilicon conductors with a gate oxide layer having a thickness between 300 .ANG. and 500 .ANG. thick. While Henderson, generally describes a double level polysilicon cell split gate electrode fabrication, the provision of a tunnel oxide layer suitable for the type of Fowler-Nordheim tunneling employed in EPROM devices is not suggested.
U.S. Pat. No. 4,646,425 of Owens et al., "Method for Making a Self-Aligned CMOS EPROM Wherein the EPROM Floating Gate and CMOS Gates are Made from One Polysilicon Layer" shows an EPROM device with floating gate electrode and control gate electrodes which are formed of N+ doped polysilicon. The gate electrodes of the N-channel EPROM device are formed over a P-substrate and a gate oxide layer.
U.S. Pat. No. 5,198,380 of Harari for "Method of Making a Highly Compact EPROM and Flash EEPROM Devices" and U.S. Pat. No. 5,268,318 of Harari for "Highly Compact EPROM and Flash EPROM Devices" describe N-channel EPROM and Flash EEPROM devices devices with floating gate electrodes and control gate electrodes composed of heavily N+ doped polysilicon with the caveat that the control gate electrode can be a silicide.
U.S. Pat. No. 4,816,883 of Baldi for "Nonvolatile Semiconductor Memory Device" describes an N-channel device (in FIG. 13 thereof) of the kind seen in FIG. 3A herein without any description of what doping is applied to the polysilicon conductors. Baldi also shows (in FIG. 1 thereof) an N-channel EPROM device of the kind seen in FIG. 3A herein with a doped polysilicon floating gate electrode and control gate electrodes without any description of what doping is applied to the polysilicon conductors.
Overall, two level polysilicon cells with a split or overlapping gate electrode are generally known and used in a variety of applications.
P-channel EEPROM and Flash EPROM devices are prone to being depleted after CHE (Channel Hot Electron) injection.